May 20th, 2021, Tokyo Japan - LeapMind Inc., a creator of the standard in edge AI (Shibuya-ku, Tokyo; CEO: Soichi Matsuda) today announced that company’s proprietary ultra-low power AI inference accelerator IP “Efficiera” was verified RTL design for ASIC/ASSP.
“By conducting the design verification this time, we were able to confirm the expected PPA (Power/Performance/Area) at the time of IP configuration.” Said Katsutoshi Yamazaki, VP of Business at LeapMind. “This is a big step for us moving forward to future LSI commercialization of Efficiera”.
Efficiera is an ultra-low power consumption AI inference accelerator IP specialized for CNN inference arithmetic processing that operates as a circuit on FPGA devices or ASIC/ASSP devices. For more information, visit here (https://leapmind.io/business/ip/).
LeapMind Inc. was founded in 2012 with the corporate philosophy of "bringing new devices that use machine learning to the world". Total investment in LeapMind to date has reached 4.99 billion yen (as of May 2021). The company's strength is in extremely low bit quantization for compact deep learning solutions. It has a proven track record of achievement with over 150 companies, centered in manufacturing including the automobile industry. It is also developing its Efficiera semiconductor IP, based on its experience in the development of both software and hardware.
Head office: Shibuya Dogenzaka Sky Building 5F, 28-1 Maruyama-cho, Shibuya-ku, Tokyo 150-0044
Representative: Soichi Matsuda, CEO
Established: December 2012
* LeapMind, Efficiera and logo are trademarks or registered trademarks of LeapMind Inc.
* The information in the press release is current as of the date of announcement.
Marketing Communication Division, Public Relations Officer, LeapMind Inc.
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Efficiera Division, Business Development Team, LeapMind Inc.
Product official website URL: https://leapmind.io/business/ip/
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